URL https://opencores.org/ocsvn/10_100m_ethernet-fifo_convertor/10_100m_ethernet-fifo_convertor/trunk

Subversion Repositories 10_100m_ethernet-fifo_convertor

[/] [10_100m_ethernet-fifo_convertor] - Rev 13

Rev	Log message	Author	Age	Path
13		antiquity	4148d 20h	/10_100m_ethernet-fifo_convertor
12	update the TxModule.v, RxModule.v and common.v	antiquity	5307d 21h	/10_100m_ethernet-fifo_convertor
11	update the TxModule.v, RxModule.v and common.v	antiquity	5307d 21h	/10_100m_ethernet-fifo_convertor
10	reorganized the structure of the directories	antiquity	5307d 22h	/10_100m_ethernet-fifo_convertor
9	Implemented the RxModule with RAM instead of register, which greatly reduced the register consumptions; fixed the loose-frame bug of TxModule	antiquity	5315d 00h	/10_100m_ethernet-fifo_convertor
8	Parameterized the code.	antiquity	5354d 02h	/10_100m_ethernet-fifo_convertor
7	Add the test file test_feedback, and add a variable to eliminate the delay between Tx and Rx	antiquity	5372d 04h	/10_100m_ethernet-fifo_convertor
6	version 0.3 correct some errors, add a new file common.v and add a new mode for frameID	antiquity	5376d 01h	/10_100m_ethernet-fifo_convertor
5	remove the 10_100m_Ethernet-fifo_convertor.doc	antiquity	5376d 01h	/10_100m_ethernet-fifo_convertor
4	Modify the RxModule.v and update the specification	antiquity	5382d 05h	/10_100m_ethernet-fifo_convertor
3	Finished the first version of the specification	antiquity	5388d 01h	/10_100m_ethernet-fifo_convertor
2	Directory structure organized. Files checked and joind together.	antiquity	5388d 02h	/10_100m_ethernet-fifo_convertor
1	The project was created and the structure was created	root	5395d 09h	/10_100m_ethernet-fifo_convertor