URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [Changelog.txt] - Rev 15

Rev	Log message	Author	Age	Path
15	Fixed LDD, STD	ale500	3605d 05h	/6809_6309_compatible_core/trunk/rtl/verilog/Changelog.txt
14	Improved speed and reduced decoder complexity	ale500	3606d 05h	/6809_6309_compatible_core/trunk/rtl/verilog/Changelog.txt
13	added missing file with test for cpu	ale500	3619d 08h	/6809_6309_compatible_core/trunk/rtl/verilog/Changelog.txt
12	Fixed inc, dec, indirect indexed, mul, shifts, h flag	ale500	3620d 05h	/6809_6309_compatible_core/trunk/rtl/verilog/Changelog.txt
11	Fixed inc, dec, clr direct, ext and ind, deca, decb	ale500	3624d 01h	/6809_6309_compatible_core/trunk/rtl/verilog/Changelog.txt
10	Fixed several extended and indirect opcodes	ale500	3627d 06h	/6809_6309_compatible_core/trunk/rtl/verilog/Changelog.txt
9	Implemented E flag, some minor optimizations	ale500	3801d 05h	/6809_6309_compatible_core/trunk/rtl/verilog/Changelog.txt
7	Added SYNC, Fixed EXG	ale500	3802d 04h	/6809_6309_compatible_core/trunk/rtl/verilog/Changelog.txt
6	Implemented CWAI. Minor optimizations	ale500	3806d 01h	/6809_6309_compatible_core/trunk/rtl/verilog/Changelog.txt
5	EXG/TFR Implemented	ale500	3806d 22h	/6809_6309_compatible_core/trunk/rtl/verilog/Changelog.txt
4	Bugfix and enhancements	ale500	3808d 04h	/6809_6309_compatible_core/trunk/rtl/verilog/Changelog.txt