URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [MC6809_cpu.v] - Rev 12

Rev	Log message	Author	Age	Path
12	Fixed inc, dec, indirect indexed, mul, shifts, h flag	ale500	3627d 03h	/6809_6309_compatible_core/trunk/rtl/verilog/MC6809_cpu.v
11	Fixed inc, dec, clr direct, ext and ind, deca, decb	ale500	3630d 22h	/6809_6309_compatible_core/trunk/rtl/verilog/MC6809_cpu.v
10	Fixed several extended and indirect opcodes	ale500	3634d 03h	/6809_6309_compatible_core/trunk/rtl/verilog/MC6809_cpu.v
9	Implemented E flag, some minor optimizations	ale500	3808d 03h	/6809_6309_compatible_core/trunk/rtl/verilog/MC6809_cpu.v
7	Added SYNC, Fixed EXG	ale500	3809d 01h	/6809_6309_compatible_core/trunk/rtl/verilog/MC6809_cpu.v
6	Implemented CWAI. Minor optimizations	ale500	3812d 23h	/6809_6309_compatible_core/trunk/rtl/verilog/MC6809_cpu.v
5	EXG/TFR Implemented	ale500	3813d 19h	/6809_6309_compatible_core/trunk/rtl/verilog/MC6809_cpu.v
4	Bugfix and enhancements	ale500	3815d 01h	/6809_6309_compatible_core/trunk/rtl/verilog/MC6809_cpu.v
2	Initial version	ale500	3816d 22h	/6809_6309_compatible_core/trunk/rtl/verilog/MC6809_cpu.v