URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_tc.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5568d 01h	/8051/tags/rel_1/rtl/verilog/oc8051_tc.v
185		root	5624d 02h	/8051/tags/rel_1/rtl/verilog/oc8051_tc.v
147	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7752d 23h	/8051/tags/rel_1/rtl/verilog/oc8051_tc.v
120	defines for pherypherals added	simont	7785d 03h	/8051/tags/rel_1/rtl/verilog/oc8051_tc.v
116	change sfr's interface.	simont	7788d 01h	/8051/tags/rel_1/rtl/verilog/oc8051_tc.v
112	change timers to meet timing specifications (add divider with 12)	simont	7791d 05h	/8051/tags/rel_1/rtl/verilog/oc8051_tc.v
82	replace some modules	simont	7872d 02h	/8051/tags/rel_1/rtl/verilog/oc8051_tc.v
46	prepared header	simont	7976d 22h	/8051/tags/rel_1/rtl/verilog/oc8051_tc.v
17	fix some bugs	simont	8021d 02h	/8051/tags/rel_1/rtl/verilog/oc8051_tc.v
4	Code repaired to satisfy the linter; testbech fails	markom	8024d 05h	/8051/tags/rel_1/rtl/verilog/oc8051_tc.v
2	Initial CVS import	simont	8040d 02h	/8051/tags/rel_1/rtl/verilog/oc8051_tc.v