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[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_top.v] - Rev 144

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Rev Log message Author Age Path
144 chsnge comp.des to des1 simont 7758d 02h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7759d 05h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
139 add aditional alu destination to solve critical path. simont 7759d 23h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
134 fix bug in case execution of two data dependent instructions. simont 7766d 03h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
132 change branch instruction execution (reduse needed clock periods). simont 7769d 21h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
122 deifne OC8051_ROM added simont 7784d 04h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
120 defines for pherypherals added simont 7785d 02h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
118 change wr_sft to 2 bit wire. simont 7785d 22h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
117 Register oc8051_sfr dato output, add signal wait_data. simont 7785d 23h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
107 Include instruction cache. simont 7791d 19h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
102 raname signals. simont 7792d 23h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
82 replace some modules simont 7872d 00h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
76 add module oc8051_sfr, 256 bytes internal ram simont 7940d 21h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
72 fix bug in interface to external data ram simont 7949d 00h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
62 fix bugs in instruction interface simont 7953d 22h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
54 cahnge interface to instruction rom simont 7959d 20h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
46 prepared header simont 7976d 21h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
37 added signals ack, stb and cyc simont 8003d 23h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
28 remove syn signal simont 8015d 03h /8051/tags/rel_1/rtl/verilog/oc8051_top.v
26 main divider logic was optimized not optimized by compiler, so I did it by hand markom 8015d 05h /8051/tags/rel_1/rtl/verilog/oc8051_top.v

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