URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [rtl/] [verilog/] [oc8051_top.v] - Rev 62

Rev	Log message	Author	Age	Path
62	fix bugs in instruction interface	simont	7953d 22h	/8051/tags/rel_1/rtl/verilog/oc8051_top.v
54	cahnge interface to instruction rom	simont	7959d 20h	/8051/tags/rel_1/rtl/verilog/oc8051_top.v
46	prepared header	simont	7976d 21h	/8051/tags/rel_1/rtl/verilog/oc8051_top.v
37	added signals ack, stb and cyc	simont	8003d 23h	/8051/tags/rel_1/rtl/verilog/oc8051_top.v
28	remove syn signal	simont	8015d 03h	/8051/tags/rel_1/rtl/verilog/oc8051_top.v
26	main divider logic was optimized not optimized by compiler, so I did it by hand	markom	8015d 05h	/8051/tags/rel_1/rtl/verilog/oc8051_top.v
19	combinatorial loop removed	simont	8017d 19h	/8051/tags/rel_1/rtl/verilog/oc8051_top.v
17	fix some bugs	simont	8021d 01h	/8051/tags/rel_1/rtl/verilog/oc8051_top.v
12	des1_r in alu port list	simont	8021d 23h	/8051/tags/rel_1/rtl/verilog/oc8051_top.v
9	removed unused compare states	markom	8023d 22h	/8051/tags/rel_1/rtl/verilog/oc8051_top.v
8	some IDS optimizations	markom	8023d 22h	/8051/tags/rel_1/rtl/verilog/oc8051_top.v
7	immediate1 & immediate2 registers moved to oc8051_immediate_sel	markom	8023d 23h	/8051/tags/rel_1/rtl/verilog/oc8051_top.v
5	more linter corrections; 2 tests still fail	markom	8024d 02h	/8051/tags/rel_1/rtl/verilog/oc8051_top.v
4	Code repaired to satisfy the linter; testbech fails	markom	8024d 03h	/8051/tags/rel_1/rtl/verilog/oc8051_top.v
2	Initial CVS import	simont	8040d 01h	/8051/tags/rel_1/rtl/verilog/oc8051_top.v