URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1/] [rtl] - Rev 62

Rev	Log message	Author	Age	Path
62	fix bugs in instruction interface	simont	7939d 03h	/8051/tags/rel_1/rtl
54	cahnge interface to instruction rom	simont	7945d 01h	/8051/tags/rel_1/rtl
47	remove unused files	simont	7962d 02h	/8051/tags/rel_1/rtl
46	prepared header	simont	7962d 02h	/8051/tags/rel_1/rtl
45	prepared header	simont	7962d 03h	/8051/tags/rel_1/rtl
44	prepared header	simont	7962d 03h	/8051/tags/rel_1/rtl
41	remove unused files	simont	7962d 05h	/8051/tags/rel_1/rtl
40	added sigals for interacting with external ram	simont	7982d 06h	/8051/tags/rel_1/rtl
38	fix some bugs	simont	7989d 05h	/8051/tags/rel_1/rtl
37	added signals ack, stb and cyc	simont	7989d 05h	/8051/tags/rel_1/rtl
36	fix bugs in mode 0	simont	7989d 05h	/8051/tags/rel_1/rtl
32	overflow repaired	simont	7990d 09h	/8051/tags/rel_1/rtl
31	fix some bugs	simont	7997d 02h	/8051/tags/rel_1/rtl
30	mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32	simont	8000d 08h	/8051/tags/rel_1/rtl
29	fix some bugs	simont	8000d 09h	/8051/tags/rel_1/rtl
28	remove syn signal	simont	8000d 09h	/8051/tags/rel_1/rtl
27	fix some bugs	simont	8000d 09h	/8051/tags/rel_1/rtl
26	main divider logic was optimized not optimized by compiler, so I did it by hand	markom	8000d 11h	/8051/tags/rel_1/rtl
25	divider and multiplier pass test	markom	8001d 05h	/8051/tags/rel_1/rtl
23	mul & div use 4 clocks	simont	8002d 01h	/8051/tags/rel_1/rtl