URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1] - Rev 104

Rev	Log message	Author	Age	Path
104	use generic_dpram	simont	7775d 18h	/8051/tags/rel_1
103	rename signals	simont	7775d 19h	/8051/tags/rel_1
102	raname signals.	simont	7775d 19h	/8051/tags/rel_1
101	initial inport	simont	7775d 22h	/8051/tags/rel_1
100	use \	simont	7775d 22h	/8051/tags/rel_1
99	change directory structure	simont	7775d 22h	/8051/tags/rel_1
98	move to rtl/verilog	simont	7775d 22h	/8051/tags/rel_1
97	initial inport	simont	7775d 22h	/8051/tags/rel_1
96	initial import	simont	7775d 23h	/8051/tags/rel_1
95	updating...	simont	7775d 23h	/8051/tags/rel_1
94	fix bug.	simont	7775d 23h	/8051/tags/rel_1
93	OC8051_XILINX_RAM added	simont	7775d 23h	/8051/tags/rel_1
92	initial inport	simont	7775d 23h	/8051/tags/rel_1
91	* empty log message *	simont	7775d 23h	/8051/tags/rel_1
90	change module name.	simont	7780d 16h	/8051/tags/rel_1
89	Replaced oc8051_ram by generic_dpram.	rherveille	7841d 20h	/8051/tags/rel_1
88	fix bugs	simont	7846d 20h	/8051/tags/rel_1
87	add include oc8051_defines.v	simont	7846d 20h	/8051/tags/rel_1
86	initial input	simont	7846d 20h	/8051/tags/rel_1
85	prepare bugs	simont	7846d 20h	/8051/tags/rel_1