URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1] - Rev 120

Rev	Log message	Author	Age	Path
120	defines for pherypherals added	simont	7767d 17h	/8051/tags/rel_1
119	remove signal sbuf_txd [12:11]	simont	7767d 21h	/8051/tags/rel_1
118	change wr_sft to 2 bit wire.	simont	7768d 14h	/8051/tags/rel_1
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7768d 14h	/8051/tags/rel_1
116	change sfr's interface.	simont	7770d 15h	/8051/tags/rel_1
115	change uart to meet timing.	simont	7770d 17h	/8051/tags/rel_1
114	remove t2mod register	simont	7773d 19h	/8051/tags/rel_1
113	signal prsc_ow added.	simont	7773d 19h	/8051/tags/rel_1
112	change timers to meet timing specifications (add divider with 12)	simont	7773d 19h	/8051/tags/rel_1
111	Remove instruction cache and wb_interface	simont	7774d 11h	/8051/tags/rel_1
110	change adr_i and adr_o length.	simont	7774d 11h	/8051/tags/rel_1
109	add `include "oc8051_defines.v"	simont	7774d 11h	/8051/tags/rel_1
108	fix some bugs, use oc8051_cache_ram.	simont	7774d 11h	/8051/tags/rel_1
107	Include instruction cache.	simont	7774d 11h	/8051/tags/rel_1
106	generic_dpram used	simont	7775d 14h	/8051/tags/rel_1
105	generic_dpram used	simont	7775d 14h	/8051/tags/rel_1
104	use generic_dpram	simont	7775d 14h	/8051/tags/rel_1
103	rename signals	simont	7775d 15h	/8051/tags/rel_1
102	raname signals.	simont	7775d 15h	/8051/tags/rel_1
101	initial inport	simont	7775d 18h	/8051/tags/rel_1