URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_1] - Rev 87

Rev	Log message	Author	Age	Path
87	add include oc8051_defines.v	simont	7910d 02h	/8051/tags/rel_1
86	initial input	simont	7910d 02h	/8051/tags/rel_1
85	prepare bugs	simont	7910d 02h	/8051/tags/rel_1
84	remove wb_bus_mon	simont	7918d 01h	/8051/tags/rel_1
83	replace some modules	simont	7918d 01h	/8051/tags/rel_1
82	replace some modules	simont	7918d 01h	/8051/tags/rel_1
81	initial import	simont	7918d 01h	/8051/tags/rel_1
80	removing unused modules	simont	7918d 01h	/8051/tags/rel_1
79	initial import	simont	7918d 02h	/8051/tags/rel_1
78	alu with registered outputs	simont	7978d 01h	/8051/tags/rel_1
77	substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel	simont	7986d 22h	/8051/tags/rel_1
76	add module oc8051_sfr, 256 bytes internal ram	simont	7986d 22h	/8051/tags/rel_1
75	initial import	simont	7986d 22h	/8051/tags/rel_1
74	add module oc8051_wb_iinterface	simont	7994d 23h	/8051/tags/rel_1
73	initial import	simont	7994d 23h	/8051/tags/rel_1
72	fix bug in interface to external data ram	simont	7995d 01h	/8051/tags/rel_1
71	add cache	simont	7999d 00h	/8051/tags/rel_1
70	initial import	simont	7999d 00h	/8051/tags/rel_1
69	add parameters	simont	7999d 02h	/8051/tags/rel_1
68	add instruction cache and DELAY parameters for external ram, rom	simont	7999d 02h	/8051/tags/rel_1