URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_acc.v] - Rev 118

Rev	Log message	Author	Age	Path
118	change wr_sft to 2 bit wire.	simont	7769d 19h	/8051/tags/rel_12/rtl/verilog/oc8051_acc.v
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7769d 20h	/8051/tags/rel_12/rtl/verilog/oc8051_acc.v
116	change sfr's interface.	simont	7771d 20h	/8051/tags/rel_12/rtl/verilog/oc8051_acc.v
82	replace some modules	simont	7855d 21h	/8051/tags/rel_12/rtl/verilog/oc8051_acc.v
76	add module oc8051_sfr, 256 bytes internal ram	simont	7924d 18h	/8051/tags/rel_12/rtl/verilog/oc8051_acc.v
46	prepared header	simont	7960d 18h	/8051/tags/rel_12/rtl/verilog/oc8051_acc.v
38	fix some bugs	simont	7987d 20h	/8051/tags/rel_12/rtl/verilog/oc8051_acc.v
37	added signals ack, stb and cyc	simont	7987d 20h	/8051/tags/rel_12/rtl/verilog/oc8051_acc.v
22	fix some bugs	simont	8000d 16h	/8051/tags/rel_12/rtl/verilog/oc8051_acc.v
5	more linter corrections; 2 tests still fail	markom	8007d 23h	/8051/tags/rel_12/rtl/verilog/oc8051_acc.v
4	Code repaired to satisfy the linter; testbech fails	markom	8008d 00h	/8051/tags/rel_12/rtl/verilog/oc8051_acc.v
2	Initial CVS import	simont	8023d 22h	/8051/tags/rel_12/rtl/verilog/oc8051_acc.v