URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_acc.v] - Rev 76

Rev	Log message	Author	Age	Path
76	add module oc8051_sfr, 256 bytes internal ram	simont	7947d 04h	/8051/tags/rel_12/rtl/verilog/oc8051_acc.v
46	prepared header	simont	7983d 04h	/8051/tags/rel_12/rtl/verilog/oc8051_acc.v
38	fix some bugs	simont	8010d 06h	/8051/tags/rel_12/rtl/verilog/oc8051_acc.v
37	added signals ack, stb and cyc	simont	8010d 07h	/8051/tags/rel_12/rtl/verilog/oc8051_acc.v
22	fix some bugs	simont	8023d 02h	/8051/tags/rel_12/rtl/verilog/oc8051_acc.v
5	more linter corrections; 2 tests still fail	markom	8030d 09h	/8051/tags/rel_12/rtl/verilog/oc8051_acc.v
4	Code repaired to satisfy the linter; testbech fails	markom	8030d 10h	/8051/tags/rel_12/rtl/verilog/oc8051_acc.v
2	Initial CVS import	simont	8046d 08h	/8051/tags/rel_12/rtl/verilog/oc8051_acc.v