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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_decoder.v] - Rev 142

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142 optimize state machine. simont 7743d 00h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7743d 02h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
139 add aditional alu destination to solve critical path. simont 7743d 20h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
132 change branch instruction execution (reduse needed clock periods). simont 7753d 18h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
118 change wr_sft to 2 bit wire. simont 7769d 19h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
117 Register oc8051_sfr dato output, add signal wait_data. simont 7769d 20h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
82 replace some modules simont 7855d 21h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
62 fix bugs in instruction interface simont 7937d 19h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
54 cahnge interface to instruction rom simont 7943d 17h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
46 prepared header simont 7960d 18h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
40 added sigals for interacting with external ram simont 7980d 22h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
23 mul & div use 4 clocks simont 8000d 16h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
20 multiplier and divider changed so they complete in 4 cycles markom 8001d 00h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
17 fix some bugs simont 8004d 22h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
10 % replaced with ^ in uart; some minor improvements markom 8006d 02h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
9 removed unused compare states markom 8007d 19h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
8 some IDS optimizations markom 8007d 19h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
5 more linter corrections; 2 tests still fail markom 8007d 23h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
4 Code repaired to satisfy the linter; testbech fails markom 8008d 00h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
2 Initial CVS import simont 8023d 22h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v

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