URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_decoder.v] - Rev 54

Rev	Log message	Author	Age	Path
54	cahnge interface to instruction rom	simont	7973d 16h	/8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
46	prepared header	simont	7990d 18h	/8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
40	added sigals for interacting with external ram	simont	8010d 22h	/8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
23	mul & div use 4 clocks	simont	8030d 16h	/8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
20	multiplier and divider changed so they complete in 4 cycles	markom	8030d 23h	/8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
17	fix some bugs	simont	8034d 21h	/8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
10	% replaced with ^ in uart; some minor improvements	markom	8036d 02h	/8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
9	removed unused compare states	markom	8037d 19h	/8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
8	some IDS optimizations	markom	8037d 19h	/8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
5	more linter corrections; 2 tests still fail	markom	8037d 22h	/8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
4	Code repaired to satisfy the linter; testbech fails	markom	8038d 00h	/8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
2	Initial CVS import	simont	8053d 22h	/8051/tags/rel_12/rtl/verilog/oc8051_decoder.v