URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_icache.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5546d 15h	/8051/tags/rel_12/rtl/verilog/oc8051_icache.v
185		root	5602d 16h	/8051/tags/rel_12/rtl/verilog/oc8051_icache.v
182	This commit was manufactured by cvs2svn to create tag 'rel_12'.		7681d 08h	/8051/tags/rel_12/rtl/verilog/oc8051_icache.v
179	add /* synopsys xx_case */ to case statments.	simont	7681d 09h	/8051/tags/rel_12/rtl/verilog/oc8051_icache.v
174	ram modules added.	simont	7692d 16h	/8051/tags/rel_12/rtl/verilog/oc8051_icache.v
137	change to fit xrom.	simont	7738d 20h	/8051/tags/rel_12/rtl/verilog/oc8051_icache.v
108	fix some bugs, use oc8051_cache_ram.	simont	7770d 11h	/8051/tags/rel_12/rtl/verilog/oc8051_icache.v
94	fix bug.	simont	7771d 19h	/8051/tags/rel_12/rtl/verilog/oc8051_icache.v
88	fix bugs	simont	7842d 16h	/8051/tags/rel_12/rtl/verilog/oc8051_icache.v
82	replace some modules	simont	7850d 16h	/8051/tags/rel_12/rtl/verilog/oc8051_icache.v
67	add parameters for instruction cache	simont	7931d 17h	/8051/tags/rel_12/rtl/verilog/oc8051_icache.v
62	fix bugs in instruction interface	simont	7932d 13h	/8051/tags/rel_12/rtl/verilog/oc8051_icache.v