URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_int.v] - Rev 90

Rev	Log message	Author	Age	Path
90	change module name.	simont	7776d 14h	/8051/tags/rel_12/rtl/verilog/oc8051_int.v
82	replace some modules	simont	7850d 18h	/8051/tags/rel_12/rtl/verilog/oc8051_int.v
46	prepared header	simont	7955d 15h	/8051/tags/rel_12/rtl/verilog/oc8051_int.v
22	fix some bugs	simont	7995d 13h	/8051/tags/rel_12/rtl/verilog/oc8051_int.v
17	fix some bugs	simont	7999d 18h	/8051/tags/rel_12/rtl/verilog/oc8051_int.v
4	Code repaired to satisfy the linter; testbech fails	markom	8002d 21h	/8051/tags/rel_12/rtl/verilog/oc8051_int.v
2	Initial CVS import	simont	8018d 19h	/8051/tags/rel_12/rtl/verilog/oc8051_int.v