URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_memory_interface.v] - Rev 149

Rev	Log message	Author	Age	Path
149	pipelined acces to axternal instruction interface added.	simont	7709d 15h	/8051/tags/rel_12/rtl/verilog/oc8051_memory_interface.v
146	fix bug in movc intruction.	simont	7731d 15h	/8051/tags/rel_12/rtl/verilog/oc8051_memory_interface.v
140	cahnge assigment to pc_wait (remove istb_o)	simont	7737d 22h	/8051/tags/rel_12/rtl/verilog/oc8051_memory_interface.v
139	add aditional alu destination to solve critical path.	simont	7738d 16h	/8051/tags/rel_12/rtl/verilog/oc8051_memory_interface.v
132	change branch instruction execution (reduse needed clock periods).	simont	7748d 15h	/8051/tags/rel_12/rtl/verilog/oc8051_memory_interface.v
128	chance idat_ir to 24 bit wide	simont	7757d 22h	/8051/tags/rel_12/rtl/verilog/oc8051_memory_interface.v
121	Change pc add value from 23'h to 16'h	simont	7762d 22h	/8051/tags/rel_12/rtl/verilog/oc8051_memory_interface.v
118	change wr_sft to 2 bit wire.	simont	7764d 16h	/8051/tags/rel_12/rtl/verilog/oc8051_memory_interface.v
81	initial import	simont	7850d 18h	/8051/tags/rel_12/rtl/verilog/oc8051_memory_interface.v