URL https://opencores.org/ocsvn/8051/8051/trunk

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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_multiply.v] - Rev 182

Rev	Log message	Author	Age	Path
182	This commit was manufactured by cvs2svn to create tag 'rel_12'.		7708d 21h	/8051/tags/rel_12/rtl/verilog/oc8051_multiply.v
95	updating...	simont	7799d 08h	/8051/tags/rel_12/rtl/verilog/oc8051_multiply.v
46	prepared header	simont	7983d 02h	/8051/tags/rel_12/rtl/verilog/oc8051_multiply.v
32	overflow repaired	simont	8011d 09h	/8051/tags/rel_12/rtl/verilog/oc8051_multiply.v
25	divider and multiplier pass test	markom	8022d 05h	/8051/tags/rel_12/rtl/verilog/oc8051_multiply.v
21	mul bug fixed	markom	8023d 05h	/8051/tags/rel_12/rtl/verilog/oc8051_multiply.v
20	multiplier and divider changed so they complete in 4 cycles	markom	8023d 08h	/8051/tags/rel_12/rtl/verilog/oc8051_multiply.v
5	more linter corrections; 2 tests still fail	markom	8030d 06h	/8051/tags/rel_12/rtl/verilog/oc8051_multiply.v
4	Code repaired to satisfy the linter; testbech fails	markom	8030d 08h	/8051/tags/rel_12/rtl/verilog/oc8051_multiply.v
2	Initial CVS import	simont	8046d 06h	/8051/tags/rel_12/rtl/verilog/oc8051_multiply.v