URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_ports.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5546d 15h	/8051/tags/rel_12/rtl/verilog/oc8051_ports.v
185		root	5602d 16h	/8051/tags/rel_12/rtl/verilog/oc8051_ports.v
182	This commit was manufactured by cvs2svn to create tag 'rel_12'.		7681d 09h	/8051/tags/rel_12/rtl/verilog/oc8051_ports.v
179	add /* synopsys xx_case */ to case statments.	simont	7681d 10h	/8051/tags/rel_12/rtl/verilog/oc8051_ports.v
120	defines for pherypherals added	simont	7763d 18h	/8051/tags/rel_12/rtl/verilog/oc8051_ports.v
116	change sfr's interface.	simont	7766d 15h	/8051/tags/rel_12/rtl/verilog/oc8051_ports.v
82	replace some modules	simont	7850d 16h	/8051/tags/rel_12/rtl/verilog/oc8051_ports.v
46	prepared header	simont	7955d 13h	/8051/tags/rel_12/rtl/verilog/oc8051_ports.v
22	fix some bugs	simont	7995d 11h	/8051/tags/rel_12/rtl/verilog/oc8051_ports.v
15	commbinatorial loop removed	simont	7999d 17h	/8051/tags/rel_12/rtl/verilog/oc8051_ports.v
5	more linter corrections; 2 tests still fail	markom	8002d 17h	/8051/tags/rel_12/rtl/verilog/oc8051_ports.v
4	Code repaired to satisfy the linter; testbech fails	markom	8002d 19h	/8051/tags/rel_12/rtl/verilog/oc8051_ports.v
2	Initial CVS import	simont	8018d 17h	/8051/tags/rel_12/rtl/verilog/oc8051_ports.v