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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_psw.v] - Rev 185

Rev	Log message	Author	Age	Path
185		root	5630d 06h	/8051/tags/rel_12/rtl/verilog/oc8051_psw.v
182	This commit was manufactured by cvs2svn to create tag 'rel_12'.		7708d 22h	/8051/tags/rel_12/rtl/verilog/oc8051_psw.v
179	add /* synopsys xx_case */ to case statments.	simont	7708d 23h	/8051/tags/rel_12/rtl/verilog/oc8051_psw.v
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7792d 04h	/8051/tags/rel_12/rtl/verilog/oc8051_psw.v
116	change sfr's interface.	simont	7794d 05h	/8051/tags/rel_12/rtl/verilog/oc8051_psw.v
82	replace some modules	simont	7878d 05h	/8051/tags/rel_12/rtl/verilog/oc8051_psw.v
76	add module oc8051_sfr, 256 bytes internal ram	simont	7947d 02h	/8051/tags/rel_12/rtl/verilog/oc8051_psw.v
46	prepared header	simont	7983d 02h	/8051/tags/rel_12/rtl/verilog/oc8051_psw.v
27	fix some bugs	simont	8021d 09h	/8051/tags/rel_12/rtl/verilog/oc8051_psw.v
22	fix some bugs	simont	8023d 00h	/8051/tags/rel_12/rtl/verilog/oc8051_psw.v
6	psw combinatorial loop removed	markom	8030d 06h	/8051/tags/rel_12/rtl/verilog/oc8051_psw.v
5	more linter corrections; 2 tests still fail	markom	8030d 07h	/8051/tags/rel_12/rtl/verilog/oc8051_psw.v
4	Code repaired to satisfy the linter; testbech fails	markom	8030d 08h	/8051/tags/rel_12/rtl/verilog/oc8051_psw.v
2	Initial CVS import	simont	8046d 06h	/8051/tags/rel_12/rtl/verilog/oc8051_psw.v