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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_ram_top.v] - Rev 185

Rev	Log message	Author	Age	Path
185		root	5630d 03h	/8051/tags/rel_12/rtl/verilog/oc8051_ram_top.v
182	This commit was manufactured by cvs2svn to create tag 'rel_12'.		7708d 19h	/8051/tags/rel_12/rtl/verilog/oc8051_ram_top.v
177	Fix bug in case of writing and reading from same address.	simont	7720d 02h	/8051/tags/rel_12/rtl/verilog/oc8051_ram_top.v
174	ram modules added.	simont	7720d 04h	/8051/tags/rel_12/rtl/verilog/oc8051_ram_top.v
172	BIST signals added.	simont	7723d 03h	/8051/tags/rel_12/rtl/verilog/oc8051_ram_top.v
105	generic_dpram used	simont	7799d 01h	/8051/tags/rel_12/rtl/verilog/oc8051_ram_top.v
95	updating...	simont	7799d 06h	/8051/tags/rel_12/rtl/verilog/oc8051_ram_top.v
89	Replaced oc8051_ram by generic_dpram.	rherveille	7865d 03h	/8051/tags/rel_12/rtl/verilog/oc8051_ram_top.v
82	replace some modules	simont	7878d 03h	/8051/tags/rel_12/rtl/verilog/oc8051_ram_top.v
46	prepared header	simont	7983d 00h	/8051/tags/rel_12/rtl/verilog/oc8051_ram_top.v
41	remove unused files	simont	7983d 02h	/8051/tags/rel_12/rtl/verilog/oc8051_ram_top.v
4	Code repaired to satisfy the linter; testbech fails	markom	8030d 06h	/8051/tags/rel_12/rtl/verilog/oc8051_ram_top.v
2	Initial CVS import	simont	8046d 04h	/8051/tags/rel_12/rtl/verilog/oc8051_ram_top.v