URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_sfr.v] - Rev 115

Rev	Log message	Author	Age	Path
115	change uart to meet timing.	simont	7794d 08h	/8051/tags/rel_12/rtl/verilog/oc8051_sfr.v
113	signal prsc_ow added.	simont	7797d 11h	/8051/tags/rel_12/rtl/verilog/oc8051_sfr.v
90	change module name.	simont	7804d 04h	/8051/tags/rel_12/rtl/verilog/oc8051_sfr.v
87	add include oc8051_defines.v	simont	7870d 08h	/8051/tags/rel_12/rtl/verilog/oc8051_sfr.v
82	replace some modules	simont	7878d 07h	/8051/tags/rel_12/rtl/verilog/oc8051_sfr.v
75	initial import	simont	7947d 04h	/8051/tags/rel_12/rtl/verilog/oc8051_sfr.v