URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_sp.v] - Rev 120

Rev	Log message	Author	Age	Path
120	defines for pherypherals added	simont	7763d 19h	/8051/tags/rel_12/rtl/verilog/oc8051_sp.v
82	replace some modules	simont	7850d 18h	/8051/tags/rel_12/rtl/verilog/oc8051_sp.v
76	add module oc8051_sfr, 256 bytes internal ram	simont	7919d 15h	/8051/tags/rel_12/rtl/verilog/oc8051_sp.v
46	prepared header	simont	7955d 14h	/8051/tags/rel_12/rtl/verilog/oc8051_sp.v
4	Code repaired to satisfy the linter; testbech fails	markom	8002d 21h	/8051/tags/rel_12/rtl/verilog/oc8051_sp.v
2	Initial CVS import	simont	8018d 18h	/8051/tags/rel_12/rtl/verilog/oc8051_sp.v