URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_tc.v] - Rev 120

Rev	Log message	Author	Age	Path
120	defines for pherypherals added	simont	7827d 00h	/8051/tags/rel_12/rtl/verilog/oc8051_tc.v
116	change sfr's interface.	simont	7829d 22h	/8051/tags/rel_12/rtl/verilog/oc8051_tc.v
112	change timers to meet timing specifications (add divider with 12)	simont	7833d 02h	/8051/tags/rel_12/rtl/verilog/oc8051_tc.v
82	replace some modules	simont	7913d 22h	/8051/tags/rel_12/rtl/verilog/oc8051_tc.v
46	prepared header	simont	8018d 19h	/8051/tags/rel_12/rtl/verilog/oc8051_tc.v
17	fix some bugs	simont	8062d 23h	/8051/tags/rel_12/rtl/verilog/oc8051_tc.v
4	Code repaired to satisfy the linter; testbech fails	markom	8066d 01h	/8051/tags/rel_12/rtl/verilog/oc8051_tc.v
2	Initial CVS import	simont	8081d 23h	/8051/tags/rel_12/rtl/verilog/oc8051_tc.v