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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_top.v] - Rev 118

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Rev Log message Author Age Path
118 change wr_sft to 2 bit wire. simont 7799d 19h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
117 Register oc8051_sfr dato output, add signal wait_data. simont 7799d 20h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
107 Include instruction cache. simont 7805d 16h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
102 raname signals. simont 7806d 20h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
82 replace some modules simont 7885d 21h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
76 add module oc8051_sfr, 256 bytes internal ram simont 7954d 18h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
72 fix bug in interface to external data ram simont 7962d 21h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
62 fix bugs in instruction interface simont 7967d 19h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
54 cahnge interface to instruction rom simont 7973d 17h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
46 prepared header simont 7990d 18h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
37 added signals ack, stb and cyc simont 8017d 20h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
28 remove syn signal simont 8029d 00h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
26 main divider logic was optimized not optimized by compiler, so I did it by hand markom 8029d 02h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
19 combinatorial loop removed simont 8031d 16h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
17 fix some bugs simont 8034d 22h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
12 des1_r in alu port list simont 8035d 20h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
9 removed unused compare states markom 8037d 19h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
8 some IDS optimizations markom 8037d 19h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
7 immediate1 & immediate2 registers moved to oc8051_immediate_sel markom 8037d 20h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
5 more linter corrections; 2 tests still fail markom 8037d 23h /8051/tags/rel_12/rtl/verilog/oc8051_top.v

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