OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_top.v] - Rev 172

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
172 BIST signals added. simont 7695d 17h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
148 include "8051_defines" added. simont 7709d 14h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
144 chsnge comp.des to des1 simont 7736d 18h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7737d 21h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
139 add aditional alu destination to solve critical path. simont 7738d 15h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
134 fix bug in case execution of two data dependent instructions. simont 7744d 20h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
132 change branch instruction execution (reduse needed clock periods). simont 7748d 14h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
122 deifne OC8051_ROM added simont 7762d 21h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
120 defines for pherypherals added simont 7763d 18h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
118 change wr_sft to 2 bit wire. simont 7764d 15h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
117 Register oc8051_sfr dato output, add signal wait_data. simont 7764d 15h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
107 Include instruction cache. simont 7770d 12h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
102 raname signals. simont 7771d 16h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
82 replace some modules simont 7850d 17h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
76 add module oc8051_sfr, 256 bytes internal ram simont 7919d 14h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
72 fix bug in interface to external data ram simont 7927d 16h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
62 fix bugs in instruction interface simont 7932d 14h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
54 cahnge interface to instruction rom simont 7938d 12h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
46 prepared header simont 7955d 13h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
37 added signals ack, stb and cyc simont 7982d 16h /8051/tags/rel_12/rtl/verilog/oc8051_top.v

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.