URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_top.v] - Rev 54

Rev	Log message	Author	Age	Path
54	cahnge interface to instruction rom	simont	7966d 05h	/8051/tags/rel_12/rtl/verilog/oc8051_top.v
46	prepared header	simont	7983d 06h	/8051/tags/rel_12/rtl/verilog/oc8051_top.v
37	added signals ack, stb and cyc	simont	8010d 08h	/8051/tags/rel_12/rtl/verilog/oc8051_top.v
28	remove syn signal	simont	8021d 12h	/8051/tags/rel_12/rtl/verilog/oc8051_top.v
26	main divider logic was optimized not optimized by compiler, so I did it by hand	markom	8021d 14h	/8051/tags/rel_12/rtl/verilog/oc8051_top.v
19	combinatorial loop removed	simont	8024d 04h	/8051/tags/rel_12/rtl/verilog/oc8051_top.v
17	fix some bugs	simont	8027d 10h	/8051/tags/rel_12/rtl/verilog/oc8051_top.v
12	des1_r in alu port list	simont	8028d 08h	/8051/tags/rel_12/rtl/verilog/oc8051_top.v
9	removed unused compare states	markom	8030d 07h	/8051/tags/rel_12/rtl/verilog/oc8051_top.v
8	some IDS optimizations	markom	8030d 07h	/8051/tags/rel_12/rtl/verilog/oc8051_top.v
7	immediate1 & immediate2 registers moved to oc8051_immediate_sel	markom	8030d 08h	/8051/tags/rel_12/rtl/verilog/oc8051_top.v
5	more linter corrections; 2 tests still fail	markom	8030d 11h	/8051/tags/rel_12/rtl/verilog/oc8051_top.v
4	Code repaired to satisfy the linter; testbech fails	markom	8030d 12h	/8051/tags/rel_12/rtl/verilog/oc8051_top.v
2	Initial CVS import	simont	8046d 10h	/8051/tags/rel_12/rtl/verilog/oc8051_top.v