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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_top.v] - Rev 82

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Rev Log message Author Age Path
82 replace some modules simont 7855d 21h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
76 add module oc8051_sfr, 256 bytes internal ram simont 7924d 17h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
72 fix bug in interface to external data ram simont 7932d 20h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
62 fix bugs in instruction interface simont 7937d 18h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
54 cahnge interface to instruction rom simont 7943d 16h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
46 prepared header simont 7960d 17h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
37 added signals ack, stb and cyc simont 7987d 20h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
28 remove syn signal simont 7999d 00h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
26 main divider logic was optimized not optimized by compiler, so I did it by hand markom 7999d 02h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
19 combinatorial loop removed simont 8001d 16h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
17 fix some bugs simont 8004d 21h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
12 des1_r in alu port list simont 8005d 19h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
9 removed unused compare states markom 8007d 18h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
8 some IDS optimizations markom 8007d 18h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
7 immediate1 & immediate2 registers moved to oc8051_immediate_sel markom 8007d 20h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
5 more linter corrections; 2 tests still fail markom 8007d 22h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
4 Code repaired to satisfy the linter; testbech fails markom 8008d 00h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
2 Initial CVS import simont 8023d 21h /8051/tags/rel_12/rtl/verilog/oc8051_top.v

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