URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_uart.v] - Rev 116

Rev	Log message	Author	Age	Path
116	change sfr's interface.	simont	7801d 20h	/8051/tags/rel_12/rtl/verilog/oc8051_uart.v
115	change uart to meet timing.	simont	7801d 22h	/8051/tags/rel_12/rtl/verilog/oc8051_uart.v
82	replace some modules	simont	7885d 21h	/8051/tags/rel_12/rtl/verilog/oc8051_uart.v
46	prepared header	simont	7990d 18h	/8051/tags/rel_12/rtl/verilog/oc8051_uart.v
36	fix bugs in mode 0	simont	8017d 20h	/8051/tags/rel_12/rtl/verilog/oc8051_uart.v
30	mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32	simont	8028d 23h	/8051/tags/rel_12/rtl/verilog/oc8051_uart.v
17	fix some bugs	simont	8034d 21h	/8051/tags/rel_12/rtl/verilog/oc8051_uart.v
10	% replaced with ^ in uart; some minor improvements	markom	8036d 02h	/8051/tags/rel_12/rtl/verilog/oc8051_uart.v
8	some IDS optimizations	markom	8037d 19h	/8051/tags/rel_12/rtl/verilog/oc8051_uart.v
5	more linter corrections; 2 tests still fail	markom	8037d 22h	/8051/tags/rel_12/rtl/verilog/oc8051_uart.v
4	Code repaired to satisfy the linter; testbech fails	markom	8038d 00h	/8051/tags/rel_12/rtl/verilog/oc8051_uart.v
2	Initial CVS import	simont	8053d 22h	/8051/tags/rel_12/rtl/verilog/oc8051_uart.v