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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_uart.v] - Rev 185

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185 root 5630d 07h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
182 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7709d 00h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
179 add /* synopsys xx_case */ to case statments. simont 7709d 01h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
135 prepared start of receiving if ren is not active. simont 7772d 10h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
119 remove signal sbuf_txd [12:11] simont 7791d 12h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
116 change sfr's interface. simont 7794d 06h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
115 change uart to meet timing. simont 7794d 08h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
82 replace some modules simont 7878d 07h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
46 prepared header simont 7983d 04h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
36 fix bugs in mode 0 simont 8010d 06h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
30 mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32 simont 8021d 09h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
17 fix some bugs simont 8027d 08h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
10 % replaced with ^ in uart; some minor improvements markom 8028d 12h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
8 some IDS optimizations markom 8030d 05h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
5 more linter corrections; 2 tests still fail markom 8030d 08h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
4 Code repaired to satisfy the linter; testbech fails markom 8030d 10h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v
2 Initial CVS import simont 8046d 08h /8051/tags/rel_12/rtl/verilog/oc8051_uart.v

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