URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_wb_iinterface.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5546d 13h	/8051/tags/rel_12/rtl/verilog/oc8051_wb_iinterface.v
185		root	5602d 14h	/8051/tags/rel_12/rtl/verilog/oc8051_wb_iinterface.v
182	This commit was manufactured by cvs2svn to create tag 'rel_12'.		7681d 06h	/8051/tags/rel_12/rtl/verilog/oc8051_wb_iinterface.v
138	Change buffering to save one clock per instruction.	simont	7738d 12h	/8051/tags/rel_12/rtl/verilog/oc8051_wb_iinterface.v
136	registering outputs.	simont	7738d 18h	/8051/tags/rel_12/rtl/verilog/oc8051_wb_iinterface.v
127	fix bug (cyc_o and stb_o)	simont	7757d 18h	/8051/tags/rel_12/rtl/verilog/oc8051_wb_iinterface.v
110	change adr_i and adr_o length.	simont	7770d 09h	/8051/tags/rel_12/rtl/verilog/oc8051_wb_iinterface.v
82	replace some modules	simont	7850d 14h	/8051/tags/rel_12/rtl/verilog/oc8051_wb_iinterface.v
73	initial import	simont	7927d 12h	/8051/tags/rel_12/rtl/verilog/oc8051_wb_iinterface.v