URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl] - Rev 105

Rev	Log message	Author	Age	Path
105	generic_dpram used	simont	7831d 08h	/8051/tags/rel_12/rtl
104	use generic_dpram	simont	7831d 08h	/8051/tags/rel_12/rtl
102	raname signals.	simont	7831d 09h	/8051/tags/rel_12/rtl
95	updating...	simont	7831d 13h	/8051/tags/rel_12/rtl
94	fix bug.	simont	7831d 13h	/8051/tags/rel_12/rtl
93	OC8051_XILINX_RAM added	simont	7831d 13h	/8051/tags/rel_12/rtl
92	initial inport	simont	7831d 13h	/8051/tags/rel_12/rtl
90	change module name.	simont	7836d 06h	/8051/tags/rel_12/rtl
89	Replaced oc8051_ram by generic_dpram.	rherveille	7897d 10h	/8051/tags/rel_12/rtl
88	fix bugs	simont	7902d 10h	/8051/tags/rel_12/rtl
87	add include oc8051_defines.v	simont	7902d 10h	/8051/tags/rel_12/rtl
82	replace some modules	simont	7910d 10h	/8051/tags/rel_12/rtl
81	initial import	simont	7910d 10h	/8051/tags/rel_12/rtl
80	removing unused modules	simont	7910d 10h	/8051/tags/rel_12/rtl
78	alu with registered outputs	simont	7970d 10h	/8051/tags/rel_12/rtl
77	substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel	simont	7979d 07h	/8051/tags/rel_12/rtl
76	add module oc8051_sfr, 256 bytes internal ram	simont	7979d 07h	/8051/tags/rel_12/rtl
75	initial import	simont	7979d 07h	/8051/tags/rel_12/rtl
73	initial import	simont	7987d 07h	/8051/tags/rel_12/rtl
72	fix bug in interface to external data ram	simont	7987d 09h	/8051/tags/rel_12/rtl