URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl] - Rev 112

Rev	Log message	Author	Age	Path
112	change timers to meet timing specifications (add divider with 12)	simont	7792d 10h	/8051/tags/rel_12/rtl
110	change adr_i and adr_o length.	simont	7793d 01h	/8051/tags/rel_12/rtl
109	add `include "oc8051_defines.v"	simont	7793d 01h	/8051/tags/rel_12/rtl
108	fix some bugs, use oc8051_cache_ram.	simont	7793d 01h	/8051/tags/rel_12/rtl
107	Include instruction cache.	simont	7793d 01h	/8051/tags/rel_12/rtl
105	generic_dpram used	simont	7794d 04h	/8051/tags/rel_12/rtl
104	use generic_dpram	simont	7794d 04h	/8051/tags/rel_12/rtl
102	raname signals.	simont	7794d 05h	/8051/tags/rel_12/rtl
95	updating...	simont	7794d 09h	/8051/tags/rel_12/rtl
94	fix bug.	simont	7794d 09h	/8051/tags/rel_12/rtl
93	OC8051_XILINX_RAM added	simont	7794d 09h	/8051/tags/rel_12/rtl
92	initial inport	simont	7794d 09h	/8051/tags/rel_12/rtl
90	change module name.	simont	7799d 03h	/8051/tags/rel_12/rtl
89	Replaced oc8051_ram by generic_dpram.	rherveille	7860d 06h	/8051/tags/rel_12/rtl
88	fix bugs	simont	7865d 06h	/8051/tags/rel_12/rtl
87	add include oc8051_defines.v	simont	7865d 07h	/8051/tags/rel_12/rtl
82	replace some modules	simont	7873d 06h	/8051/tags/rel_12/rtl
81	initial import	simont	7873d 06h	/8051/tags/rel_12/rtl
80	removing unused modules	simont	7873d 06h	/8051/tags/rel_12/rtl
78	alu with registered outputs	simont	7933d 06h	/8051/tags/rel_12/rtl