URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl] - Rev 128

Rev	Log message	Author	Age	Path
128	chance idat_ir to 24 bit wide	simont	7780d 11h	/8051/tags/rel_12/rtl
127	fix bug (cyc_o and stb_o)	simont	7780d 11h	/8051/tags/rel_12/rtl
126	define OC8051_XILINX_RAMB added	simont	7780d 11h	/8051/tags/rel_12/rtl
123	fiz bug iv pcs operation.	simont	7782d 06h	/8051/tags/rel_12/rtl
122	deifne OC8051_ROM added	simont	7785d 11h	/8051/tags/rel_12/rtl
121	Change pc add value from 23'h to 16'h	simont	7785d 11h	/8051/tags/rel_12/rtl
120	defines for pherypherals added	simont	7786d 08h	/8051/tags/rel_12/rtl
119	remove signal sbuf_txd [12:11]	simont	7786d 12h	/8051/tags/rel_12/rtl
118	change wr_sft to 2 bit wire.	simont	7787d 04h	/8051/tags/rel_12/rtl
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7787d 05h	/8051/tags/rel_12/rtl
116	change sfr's interface.	simont	7789d 06h	/8051/tags/rel_12/rtl
115	change uart to meet timing.	simont	7789d 07h	/8051/tags/rel_12/rtl
114	remove t2mod register	simont	7792d 10h	/8051/tags/rel_12/rtl
113	signal prsc_ow added.	simont	7792d 10h	/8051/tags/rel_12/rtl
112	change timers to meet timing specifications (add divider with 12)	simont	7792d 10h	/8051/tags/rel_12/rtl
110	change adr_i and adr_o length.	simont	7793d 01h	/8051/tags/rel_12/rtl
109	add `include "oc8051_defines.v"	simont	7793d 01h	/8051/tags/rel_12/rtl
108	fix some bugs, use oc8051_cache_ram.	simont	7793d 01h	/8051/tags/rel_12/rtl
107	Include instruction cache.	simont	7793d 01h	/8051/tags/rel_12/rtl
105	generic_dpram used	simont	7794d 04h	/8051/tags/rel_12/rtl