URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [rtl] - Rev 95

Rev	Log message	Author	Age	Path
95	updating...	simont	7794d 15h	/8051/tags/rel_12/rtl
94	fix bug.	simont	7794d 15h	/8051/tags/rel_12/rtl
93	OC8051_XILINX_RAM added	simont	7794d 15h	/8051/tags/rel_12/rtl
92	initial inport	simont	7794d 15h	/8051/tags/rel_12/rtl
90	change module name.	simont	7799d 09h	/8051/tags/rel_12/rtl
89	Replaced oc8051_ram by generic_dpram.	rherveille	7860d 12h	/8051/tags/rel_12/rtl
88	fix bugs	simont	7865d 12h	/8051/tags/rel_12/rtl
87	add include oc8051_defines.v	simont	7865d 13h	/8051/tags/rel_12/rtl
82	replace some modules	simont	7873d 12h	/8051/tags/rel_12/rtl
81	initial import	simont	7873d 12h	/8051/tags/rel_12/rtl
80	removing unused modules	simont	7873d 12h	/8051/tags/rel_12/rtl
78	alu with registered outputs	simont	7933d 12h	/8051/tags/rel_12/rtl
77	substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel	simont	7942d 09h	/8051/tags/rel_12/rtl
76	add module oc8051_sfr, 256 bytes internal ram	simont	7942d 09h	/8051/tags/rel_12/rtl
75	initial import	simont	7942d 09h	/8051/tags/rel_12/rtl
73	initial import	simont	7950d 10h	/8051/tags/rel_12/rtl
72	fix bug in interface to external data ram	simont	7950d 11h	/8051/tags/rel_12/rtl
67	add parameters for instruction cache	simont	7954d 13h	/8051/tags/rel_12/rtl
62	fix bugs in instruction interface	simont	7955d 09h	/8051/tags/rel_12/rtl
54	cahnge interface to instruction rom	simont	7961d 08h	/8051/tags/rel_12/rtl