URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12/] [syn/] [src/] [verilog/] [oc8051_fpga_top.v] - Rev 71

Rev	Log message	Author	Age	Path
71	add cache	simont	7932d 01h	/8051/tags/rel_12/syn/src/verilog/oc8051_fpga_top.v
46	prepared header	simont	7955d 22h	/8051/tags/rel_12/syn/src/verilog/oc8051_fpga_top.v
39	added signals ack, stb and cyc	simont	7983d 00h	/8051/tags/rel_12/syn/src/verilog/oc8051_fpga_top.v
2	Initial CVS import	simont	8019d 02h	/8051/tags/rel_12/syn/src/verilog/oc8051_fpga_top.v