URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_12] - Rev 157

Rev	Log message	Author	Age	Path
157	change data output.	simont	7730d 23h	/8051/tags/rel_12
156	add FREQ paremeter.	simont	7730d 23h	/8051/tags/rel_12
155	add aditional tests.	simont	7730d 23h	/8051/tags/rel_12
154	File name fixed.	simont	7731d 18h	/8051/tags/rel_12
153	`ifdef added.	simont	7732d 17h	/8051/tags/rel_12
152	sub_result output added.	simont	7732d 17h	/8051/tags/rel_12
151	remove pc_r register.	simont	7732d 17h	/8051/tags/rel_12
150	fix some bugs.	simont	7732d 17h	/8051/tags/rel_12
149	pipelined acces to axternal instruction interface added.	simont	7732d 17h	/8051/tags/rel_12
148	include "8051_defines" added.	simont	7732d 18h	/8051/tags/rel_12
146	fix bug in movc intruction.	simont	7754d 18h	/8051/tags/rel_12
145	fix bug in case of sequence of inc dptr instrucitons.	simont	7759d 22h	/8051/tags/rel_12
144	chsnge comp.des to des1	simont	7759d 22h	/8051/tags/rel_12
143	add wire sub_result, conect it to des_acc and des1.	simont	7759d 22h	/8051/tags/rel_12
142	optimize state machine.	simont	7760d 23h	/8051/tags/rel_12
141	remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.	simont	7761d 01h	/8051/tags/rel_12
140	cahnge assigment to pc_wait (remove istb_o)	simont	7761d 01h	/8051/tags/rel_12
139	add aditional alu destination to solve critical path.	simont	7761d 19h	/8051/tags/rel_12
138	Change buffering to save one clock per instruction.	simont	7761d 19h	/8051/tags/rel_12
137	change to fit xrom.	simont	7762d 00h	/8051/tags/rel_12