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[/] [8051/] [tags/] [rel_2/] [bench/] [verilog/] [oc8051_tb.v] - Rev 186

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186 root 5605d 01h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
185 root 5661d 02h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
180 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7739d 20h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
167 add readmem for ea. simont 7765d 06h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
166 Change test monitor from ports to external data memory. simont 7765d 23h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
165 remove dumpvars. simont 7766d 03h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
156 add FREQ paremeter. simont 7766d 05h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
124 add support for external rom from xilinx ramb4 simont 7816d 06h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
120 defines for pherypherals added simont 7822d 04h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
111 Remove instruction cache and wb_interface simont 7828d 21h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
103 rename signals simont 7830d 01h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
84 remove wb_bus_mon simont 7909d 02h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
74 add module oc8051_wb_iinterface simont 7986d 00h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
68 add instruction cache and DELAY parameters for external ram, rom simont 7990d 03h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
59 add external rom simont 7996d 21h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
46 prepared header simont 8013d 23h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
37 added signals ack, stb and cyc simont 8041d 01h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
4 Code repaired to satisfy the linter; testbech fails markom 8061d 05h /8051/tags/rel_2/bench/verilog/oc8051_tb.v
2 Initial CVS import simont 8077d 03h /8051/tags/rel_2/bench/verilog/oc8051_tb.v

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