URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] [bench/] [verilog/] [oc8051_tb.v] - Rev 74

Rev	Log message	Author	Age	Path
74	add module oc8051_wb_iinterface	simont	7924d 17h	/8051/tags/rel_2/bench/verilog/oc8051_tb.v
68	add instruction cache and DELAY parameters for external ram, rom	simont	7928d 20h	/8051/tags/rel_2/bench/verilog/oc8051_tb.v
59	add external rom	simont	7935d 15h	/8051/tags/rel_2/bench/verilog/oc8051_tb.v
46	prepared header	simont	7952d 16h	/8051/tags/rel_2/bench/verilog/oc8051_tb.v
37	added signals ack, stb and cyc	simont	7979d 19h	/8051/tags/rel_2/bench/verilog/oc8051_tb.v
4	Code repaired to satisfy the linter; testbech fails	markom	7999d 23h	/8051/tags/rel_2/bench/verilog/oc8051_tb.v
2	Initial CVS import	simont	8015d 20h	/8051/tags/rel_2/bench/verilog/oc8051_tb.v