URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] [bench/] [verilog] - Rev 186

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Rev	Log message	Author	Age	Path
186		root	5547d 21h	/8051/tags/rel_2/bench/verilog
185		root	5603d 22h	/8051/tags/rel_2/bench/verilog
180	This commit was manufactured by cvs2svn to create tag 'rel_2'.		7682d 15h	/8051/tags/rel_2/bench/verilog
167	add readmem for ea.	simont	7708d 02h	/8051/tags/rel_2/bench/verilog
166	Change test monitor from ports to external data memory.	simont	7708d 19h	/8051/tags/rel_2/bench/verilog
165	remove dumpvars.	simont	7708d 23h	/8051/tags/rel_2/bench/verilog
157	change data output.	simont	7709d 01h	/8051/tags/rel_2/bench/verilog
156	add FREQ paremeter.	simont	7709d 01h	/8051/tags/rel_2/bench/verilog
125	update, add prescaler, rclk, tclk.	simont	7759d 02h	/8051/tags/rel_2/bench/verilog
124	add support for external rom from xilinx ramb4	simont	7759d 02h	/8051/tags/rel_2/bench/verilog
120	defines for pherypherals added	simont	7764d 23h	/8051/tags/rel_2/bench/verilog
111	Remove instruction cache and wb_interface	simont	7771d 17h	/8051/tags/rel_2/bench/verilog
103	rename signals	simont	7772d 21h	/8051/tags/rel_2/bench/verilog
97	initial inport	simont	7773d 00h	/8051/tags/rel_2/bench/verilog
84	remove wb_bus_mon	simont	7851d 22h	/8051/tags/rel_2/bench/verilog
74	add module oc8051_wb_iinterface	simont	7928d 19h	/8051/tags/rel_2/bench/verilog
68	add instruction cache and DELAY parameters for external ram, rom	simont	7932d 23h	/8051/tags/rel_2/bench/verilog
59	add external rom	simont	7939d 17h	/8051/tags/rel_2/bench/verilog
46	prepared header	simont	7956d 19h	/8051/tags/rel_2/bench/verilog
37	added signals ack, stb and cyc	simont	7983d 21h	/8051/tags/rel_2/bench/verilog

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Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] [bench/] [verilog] - Rev 186

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