URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] [bench/] [verilog] - Rev 111

Rev	Log message	Author	Age	Path
111	Remove instruction cache and wb_interface	simont	7771d 14h	/8051/tags/rel_2/bench/verilog
103	rename signals	simont	7772d 18h	/8051/tags/rel_2/bench/verilog
97	initial inport	simont	7772d 22h	/8051/tags/rel_2/bench/verilog
84	remove wb_bus_mon	simont	7851d 19h	/8051/tags/rel_2/bench/verilog
74	add module oc8051_wb_iinterface	simont	7928d 17h	/8051/tags/rel_2/bench/verilog
68	add instruction cache and DELAY parameters for external ram, rom	simont	7932d 20h	/8051/tags/rel_2/bench/verilog
59	add external rom	simont	7939d 14h	/8051/tags/rel_2/bench/verilog
46	prepared header	simont	7956d 16h	/8051/tags/rel_2/bench/verilog
37	added signals ack, stb and cyc	simont	7983d 18h	/8051/tags/rel_2/bench/verilog
4	Code repaired to satisfy the linter; testbech fails	markom	8003d 22h	/8051/tags/rel_2/bench/verilog
2	Initial CVS import	simont	8019d 20h	/8051/tags/rel_2/bench/verilog