URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] [rtl/] - Rev 107

Rev	Log message	Author	Age	Path
107	Include instruction cache.	simont	7772d 23h	/8051/tags/rel_2/rtl
105	generic_dpram used	simont	7774d 02h	/8051/tags/rel_2/rtl
104	use generic_dpram	simont	7774d 02h	/8051/tags/rel_2/rtl
102	raname signals.	simont	7774d 03h	/8051/tags/rel_2/rtl
95	updating...	simont	7774d 06h	/8051/tags/rel_2/rtl
94	fix bug.	simont	7774d 06h	/8051/tags/rel_2/rtl
93	OC8051_XILINX_RAM added	simont	7774d 07h	/8051/tags/rel_2/rtl
92	initial inport	simont	7774d 07h	/8051/tags/rel_2/rtl
90	change module name.	simont	7779d 00h	/8051/tags/rel_2/rtl
89	Replaced oc8051_ram by generic_dpram.	rherveille	7840d 04h	/8051/tags/rel_2/rtl
88	fix bugs	simont	7845d 04h	/8051/tags/rel_2/rtl
87	add include oc8051_defines.v	simont	7845d 04h	/8051/tags/rel_2/rtl
82	replace some modules	simont	7853d 04h	/8051/tags/rel_2/rtl
81	initial import	simont	7853d 04h	/8051/tags/rel_2/rtl
80	removing unused modules	simont	7853d 04h	/8051/tags/rel_2/rtl
78	alu with registered outputs	simont	7913d 04h	/8051/tags/rel_2/rtl
77	substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel	simont	7922d 00h	/8051/tags/rel_2/rtl
76	add module oc8051_sfr, 256 bytes internal ram	simont	7922d 00h	/8051/tags/rel_2/rtl
75	initial import	simont	7922d 00h	/8051/tags/rel_2/rtl
73	initial import	simont	7930d 01h	/8051/tags/rel_2/rtl