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[/] [8051/] [tags/] [rel_2/] [rtl/] [verilog/] [oc8051_alu.v] - Rev 186

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186 root 5572d 17h /8051/tags/rel_2/rtl/verilog/oc8051_alu.v
185 root 5628d 18h /8051/tags/rel_2/rtl/verilog/oc8051_alu.v
180 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7707d 11h /8051/tags/rel_2/rtl/verilog/oc8051_alu.v
179 add /* synopsys xx_case */ to case statments. simont 7707d 11h /8051/tags/rel_2/rtl/verilog/oc8051_alu.v
178 x replaced with 0. simont 7707d 13h /8051/tags/rel_2/rtl/verilog/oc8051_alu.v
171 fix bug in DA operation. simont 7729d 15h /8051/tags/rel_2/rtl/verilog/oc8051_alu.v
152 sub_result output added. simont 7735d 15h /8051/tags/rel_2/rtl/verilog/oc8051_alu.v
143 add wire sub_result, conect it to des_acc and des1. simont 7762d 20h /8051/tags/rel_2/rtl/verilog/oc8051_alu.v
139 add aditional alu destination to solve critical path. simont 7764d 16h /8051/tags/rel_2/rtl/verilog/oc8051_alu.v
133 fix bug in substraction. simont 7771d 00h /8051/tags/rel_2/rtl/verilog/oc8051_alu.v
132 change branch instruction execution (reduse needed clock periods). simont 7774d 15h /8051/tags/rel_2/rtl/verilog/oc8051_alu.v
123 fiz bug iv pcs operation. simont 7785d 18h /8051/tags/rel_2/rtl/verilog/oc8051_alu.v
82 replace some modules simont 7876d 18h /8051/tags/rel_2/rtl/verilog/oc8051_alu.v
46 prepared header simont 7981d 15h /8051/tags/rel_2/rtl/verilog/oc8051_alu.v
22 fix some bugs simont 8021d 13h /8051/tags/rel_2/rtl/verilog/oc8051_alu.v
11 des2_r removed simont 8026d 17h /8051/tags/rel_2/rtl/verilog/oc8051_alu.v
10 % replaced with ^ in uart; some minor improvements markom 8026d 23h /8051/tags/rel_2/rtl/verilog/oc8051_alu.v
8 some IDS optimizations markom 8028d 16h /8051/tags/rel_2/rtl/verilog/oc8051_alu.v
7 immediate1 & immediate2 registers moved to oc8051_immediate_sel markom 8028d 17h /8051/tags/rel_2/rtl/verilog/oc8051_alu.v
5 more linter corrections; 2 tests still fail markom 8028d 19h /8051/tags/rel_2/rtl/verilog/oc8051_alu.v

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