URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] [rtl] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5549d 11h	/8051/tags/rel_2/rtl
185		root	5605d 12h	/8051/tags/rel_2/rtl
180	This commit was manufactured by cvs2svn to create tag 'rel_2'.		7684d 05h	/8051/tags/rel_2/rtl
179	add /* synopsys xx_case */ to case statments.	simont	7684d 05h	/8051/tags/rel_2/rtl
178	x replaced with 0.	simont	7684d 07h	/8051/tags/rel_2/rtl
177	Fix bug in case of writing and reading from same address.	simont	7695d 10h	/8051/tags/rel_2/rtl
175	initial inport.	simont	7695d 12h	/8051/tags/rel_2/rtl
174	ram modules added.	simont	7695d 12h	/8051/tags/rel_2/rtl
173	simualtion `ifdef added	simont	7695d 12h	/8051/tags/rel_2/rtl
172	BIST signals added.	simont	7698d 12h	/8051/tags/rel_2/rtl
171	fix bug in DA operation.	simont	7706d 09h	/8051/tags/rel_2/rtl
158	fix bug.	simont	7710d 15h	/8051/tags/rel_2/rtl
153	`ifdef added.	simont	7712d 09h	/8051/tags/rel_2/rtl
152	sub_result output added.	simont	7712d 09h	/8051/tags/rel_2/rtl
151	remove pc_r register.	simont	7712d 09h	/8051/tags/rel_2/rtl
150	fix some bugs.	simont	7712d 09h	/8051/tags/rel_2/rtl
149	pipelined acces to axternal instruction interface added.	simont	7712d 09h	/8051/tags/rel_2/rtl
148	include "8051_defines" added.	simont	7712d 09h	/8051/tags/rel_2/rtl
146	fix bug in movc intruction.	simont	7734d 09h	/8051/tags/rel_2/rtl
145	fix bug in case of sequence of inc dptr instrucitons.	simont	7739d 13h	/8051/tags/rel_2/rtl