URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] [rtl] - Rev 119

Rev	Log message	Author	Age	Path
119	remove signal sbuf_txd [12:11]	simont	7767d 12h	/8051/tags/rel_2/rtl
118	change wr_sft to 2 bit wire.	simont	7768d 05h	/8051/tags/rel_2/rtl
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7768d 05h	/8051/tags/rel_2/rtl
116	change sfr's interface.	simont	7770d 06h	/8051/tags/rel_2/rtl
115	change uart to meet timing.	simont	7770d 08h	/8051/tags/rel_2/rtl
114	remove t2mod register	simont	7773d 11h	/8051/tags/rel_2/rtl
113	signal prsc_ow added.	simont	7773d 11h	/8051/tags/rel_2/rtl
112	change timers to meet timing specifications (add divider with 12)	simont	7773d 11h	/8051/tags/rel_2/rtl
110	change adr_i and adr_o length.	simont	7774d 02h	/8051/tags/rel_2/rtl
109	add `include "oc8051_defines.v"	simont	7774d 02h	/8051/tags/rel_2/rtl
108	fix some bugs, use oc8051_cache_ram.	simont	7774d 02h	/8051/tags/rel_2/rtl
107	Include instruction cache.	simont	7774d 02h	/8051/tags/rel_2/rtl
105	generic_dpram used	simont	7775d 05h	/8051/tags/rel_2/rtl
104	use generic_dpram	simont	7775d 05h	/8051/tags/rel_2/rtl
102	raname signals.	simont	7775d 06h	/8051/tags/rel_2/rtl
95	updating...	simont	7775d 10h	/8051/tags/rel_2/rtl
94	fix bug.	simont	7775d 10h	/8051/tags/rel_2/rtl
93	OC8051_XILINX_RAM added	simont	7775d 10h	/8051/tags/rel_2/rtl
92	initial inport	simont	7775d 10h	/8051/tags/rel_2/rtl
90	change module name.	simont	7780d 03h	/8051/tags/rel_2/rtl