URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2] - Rev 151

Rev	Log message	Author	Age	Path
151	remove pc_r register.	simont	7734d 05h	/8051/tags/rel_2
150	fix some bugs.	simont	7734d 05h	/8051/tags/rel_2
149	pipelined acces to axternal instruction interface added.	simont	7734d 05h	/8051/tags/rel_2
148	include "8051_defines" added.	simont	7734d 05h	/8051/tags/rel_2
146	fix bug in movc intruction.	simont	7756d 06h	/8051/tags/rel_2
145	fix bug in case of sequence of inc dptr instrucitons.	simont	7761d 10h	/8051/tags/rel_2
144	chsnge comp.des to des1	simont	7761d 10h	/8051/tags/rel_2
143	add wire sub_result, conect it to des_acc and des1.	simont	7761d 10h	/8051/tags/rel_2
142	optimize state machine.	simont	7762d 11h	/8051/tags/rel_2
141	remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.	simont	7762d 13h	/8051/tags/rel_2
140	cahnge assigment to pc_wait (remove istb_o)	simont	7762d 13h	/8051/tags/rel_2
139	add aditional alu destination to solve critical path.	simont	7763d 07h	/8051/tags/rel_2
138	Change buffering to save one clock per instruction.	simont	7763d 07h	/8051/tags/rel_2
137	change to fit xrom.	simont	7763d 12h	/8051/tags/rel_2
136	registering outputs.	simont	7763d 12h	/8051/tags/rel_2
135	prepared start of receiving if ren is not active.	simont	7769d 11h	/8051/tags/rel_2
134	fix bug in case execution of two data dependent instructions.	simont	7769d 11h	/8051/tags/rel_2
133	fix bug in substraction.	simont	7769d 14h	/8051/tags/rel_2
132	change branch instruction execution (reduse needed clock periods).	simont	7773d 05h	/8051/tags/rel_2
131	prepare programs for new timing.	simont	7773d 05h	/8051/tags/rel_2