URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk] - Rev 136

Rev	Log message	Author	Age	Path
136	registering outputs.	simont	7774d 10h	/8051/trunk
135	prepared start of receiving if ren is not active.	simont	7780d 09h	/8051/trunk
134	fix bug in case execution of two data dependent instructions.	simont	7780d 09h	/8051/trunk
133	fix bug in substraction.	simont	7780d 12h	/8051/trunk
132	change branch instruction execution (reduse needed clock periods).	simont	7784d 03h	/8051/trunk
131	prepare programs for new timing.	simont	7784d 03h	/8051/trunk
130	prepared programs for new timing.	simont	7784d 03h	/8051/trunk
129	updated...	simont	7784d 03h	/8051/trunk
128	chance idat_ir to 24 bit wide	simont	7793d 10h	/8051/trunk
127	fix bug (cyc_o and stb_o)	simont	7793d 10h	/8051/trunk
126	define OC8051_XILINX_RAMB added	simont	7793d 10h	/8051/trunk
125	update, add prescaler, rclk, tclk.	simont	7793d 11h	/8051/trunk
124	add support for external rom from xilinx ramb4	simont	7793d 11h	/8051/trunk
123	fiz bug iv pcs operation.	simont	7795d 06h	/8051/trunk
122	deifne OC8051_ROM added	simont	7798d 10h	/8051/trunk
121	Change pc add value from 23'h to 16'h	simont	7798d 10h	/8051/trunk
120	defines for pherypherals added	simont	7799d 08h	/8051/trunk
119	remove signal sbuf_txd [12:11]	simont	7799d 12h	/8051/trunk
118	change wr_sft to 2 bit wire.	simont	7800d 04h	/8051/trunk
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7800d 05h	/8051/trunk