URL https://opencores.org/ocsvn/ac97/ac97/trunk

Subversion Repositories ac97

[/] [ac97/] [trunk/] [rtl/] [verilog/] [ac97_int.v] - Rev 21

Rev	Log message	Author	Age	Path
21	Fix overrun and underrun interrupts bug The overrun and underrun did not have any logic for resetting their signals, this patch changes that so that the interrupt signal is only on when the event happens. The interrupt will be latched into the interrupt status register anyway, so keeping it high for (in worst case) one clock cycle is enough.	stekern	4727d 12h	/ac97/trunk/rtl/verilog/ac97_int.v
20		root	5524d 23h	/ac97/trunk/rtl/verilog/ac97_int.v
17	New directory structure.	root	5581d 04h	/ac97/trunk/rtl/verilog/ac97_int.v
14	Fixed a bug reported by Igor. Apparently this bug only shows up when the WB clock is very low (2x bit_clk). Updated Copyright header.	rudi	7945d 08h	/ac97/trunk/rtl/verilog/ac97_int.v
10	- Fixed the order of the thrash hold bits to match the spec. - Many minor synthesis cleanup items ...	rudi	8143d 10h	/ac97/trunk/rtl/verilog/ac97_int.v
4	- Changed to new directory structure	rudi	8357d 08h	/ac97/trunk/rtl/verilog/ac97_int.v