OpenCores
URL https://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/trunk

Subversion Repositories adv_debug_sys

[/] [adv_debug_sys/] [tags/] [ADS_RELEASE_2_5_0/] [Doc] - Rev 47

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
47 Created 2.5.0 release. nyawn 5220d 22h /adv_debug_sys/tags/ADS_RELEASE_2_5_0/Doc
42 Added (experimental) Actel UJTAG TAP core. Added JTAG serial port feature to debug hardware core and JTAG bridge program. Added more speedups for USB JTAG cables to bridge program - USB-Blaster users should now see ~30k/sec upload speeds. Updated documentation. nyawn 5233d 21h /adv_debug_sys/trunk/Doc
33 Updated top-level docs to include hi-speed mode. nyawn 5306d 13h /adv_debug_sys/trunk/Doc
14 Added support for the legacy hardware debug unit (debug_if) to adv_jtag_bridge. Re-factored adv_jtag_bridge, removed many compilation warnings. Renamed some signals in the TAP cores for clarity. Updated documents. nyawn 5521d 14h /adv_debug_sys/trunk/Doc
8 Moved sub-modules to the correct subdirectories. nyawn 5550d 14h /adv_debug_sys/trunk/Doc
5 nyawn 5550d 14h /adv_debug_sys/trunk/Doc

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.