URL https://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/trunk

Subversion Repositories adv_debug_sys

[/] [adv_debug_sys/] [tags/] [ADS_RELEASE_2_5_0/] [Hardware/] [adv_dbg_if/] [rtl/] [verilog/] [bytefifo.v] - Rev 48

Rev	Log message	Author	Age	Path
48	Created 2.5.0 release.	nyawn	5204d 23h	/adv_debug_sys/tags/ADS_RELEASE_2_5_0/Hardware/adv_dbg_if/rtl/verilog/bytefifo.v
42	Added (experimental) Actel UJTAG TAP core. Added JTAG serial port feature to debug hardware core and JTAG bridge program. Added more speedups for USB JTAG cables to bridge program - USB-Blaster users should now see ~30k/sec upload speeds. Updated documentation.	nyawn	5217d 22h	/adv_debug_sys/tags/ADS_RELEASE_2_5_0/Hardware/adv_dbg_if/rtl/verilog/bytefifo.v